Selective deposition using hydrolysis

ABSTRACT

Methods and apparatuses for selective deposition of metal oxides on metal surfaces relative to dielectric surfaces are provided. Selective deposition is achieved by exposing metal and dielectric surfaces to a blocking reagent capable of forming a hydrolyzable bond with metal while forming a non-hydrolyzable bond with the dielectric, and dipping the surfaces in water to cleave the hydrolyzable bond and leave a blocked surface on the dielectric surface, followed by depositing metal oxide selectively on the metal surface relative to the dielectric surface. Blocking reagents are deposited by wet or dry techniques and may include an alkylaminosilane or alkylchlorosilane as examples.

INCORPORATION BY REFERENCE

An Application Data Sheet is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed Application Data Sheet is incorporated by reference herein in their entireties and for all purposes.

BACKGROUND

Semiconductor device fabrication includes fabrication of microprocessors, logic, and memory devices. Such devices may be fabricated using a variety of techniques, including self-aligned patterning such as double patterning or quad patterning, gapfill processes, and other techniques. Some processes involve formation of structures that include silicon oxide and metal, such as copper. Conventional techniques for forming such structures may be limited.

SUMMARY

Provided are methods of processing substrates. One aspect involves a method of selectively depositing metal oxide on an exposed metal surface relative to a dielectric material on a substrate, the method including: (a) providing the substrate including the dielectric material and the exposed metal surface; (b) prior to depositing the metal oxide, exposing the substrate to a blocking reagent to non-selectively adsorb the blocking reagent onto both the dielectric material and the exposed metal surface; (c) after exposing the substrate to the blocking reagent and prior to depositing the metal oxide, selectively removing the blocking reagent from the exposed metal surface; and (d) selectively depositing the metal oxide on the exposed metal surface relative to the dielectric material on the substrate.

In various embodiments, selectively removing the blocking reagent is performed by contacting the substrate with water. In some embodiments, selectively removing the blocking reagent is performed by dipping the substrate in water.

In various embodiments, the blocking reagent is a silicon amide.

In various embodiments, the blocking reagent is an alkylchlorosilane. An example alkylchlorosilane has a chemical structure of Cl_(x)Si([CH₃(CH₂)_(y)])_((4-x)), where x is an integer between and including 1 and 3, and y is an integer greater than or equal to 1.

In various embodiments, the blocking reagent is an alkylaminosilane. An example alkylaminosilane has a chemical structure of [(CH₃)₂N]_(x)Si([CH₃(CH₂)_(y)])_((4-x)), where x is an integer between and including 1 and 3, and y is an integer greater than or equal to 1.

In various embodiments, the blocking reagent is provided in an aprotic polar solvent.

The blocking reagent may form a hydrolyzable bond with the exposed metal surface but does not form a hydrolyzable bond with the dielectric material.

The substrate may be exposed to the blocking reagent by dipping the substrate in a wet solution of the blocking reagent. In some embodiments, the substrate is exposed to the blocking reagent at a temperature between about 25° C. and about 100° C.

In some embodiments, the substrate is exposed to the blocking reagent at a temperature between about 60° C. and about 100° C.

In various embodiments, the substrate is exposed to the blocking reagent by introducing the blocking reagent in vapor phase. In some embodiments, the substrate is exposed to the blocking reagent at a temperature between about 100° C. and about 300° C.

In some embodiments, the substrate is exposed to the blocking reagent at a temperature between about 200° C. and about 250° C.

In various embodiments, the substrate is exposed to the blocking reagent for a duration between about 10 seconds and about 60 seconds.

In various embodiments, selectively removing the blocking reagent the substrate is performed at room temperature.

Selectively removing the blocking reagent the substrate may selectively hydrolyze bonds between the blocking reagent and the exposed metal surface.

In various embodiments, the metal oxide deposited is alumina.

In various embodiments, the metal oxide is selectively deposited on the exposed metal surface relative to the dielectric material using atomic layer deposition.

In various embodiments, the exposed metal surface comprises a metal selected from the group consisting of tungsten, titanium, and aluminum.

In various embodiments, the dielectric material comprises silicon. In some embodiments, the dielectric material is selected from the group consisting of silicon oxide, silicon nitride, carbon doped silicon oxide.

In various embodiments, the substrate is patterned.

In various embodiments, the hydrolyzing results in the exposed metal surface having a hydrogen terminated and/or hydroxyl terminated surface.

Another aspect involves a method of selectively depositing metal oxide on an exposed metal surface relative to a dielectric material on a substrate, the method including: (a) providing the substrate including the dielectric material and the exposed metal surface; (b) prior to depositing the metal oxide, exposing the substrate to a blocking reagent to non-selectively adsorb the blocking reagent onto both the dielectric material and the exposed metal surface; (c) after exposing the substrate to the blocking reagent and prior to depositing the metal oxide, contacting substrate with water to selectively remove the blocking reagent from the exposed metal surface; and (d) selectively depositing the metal oxide on the exposed metal surface relative to the dielectric material on the substrate.

These and other aspects are described further below with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a process flow diagram depicting operations for performing a method.

FIGS. 2A-2E are schematic diagrams of an example of a mechanism for selectively depositing material on an exposed metal surface relative to a dielectric surface in accordance with certain disclosed embodiments.

FIG. 3 is a timing sequence diagram showing an example of cycles in a method in accordance with certain disclosed embodiments.

FIG. 4 is a schematic diagram of an example process chamber for performing disclosed embodiments.

FIG. 5 is a schematic diagram of an example process tool for performing disclosed embodiments.

FIG. 6A is a graph depicting thickness of film deposited over particular numbers of ALD cycles for deposition on a tungsten surface and a silicon oxide surface.

FIG. 6B is a graph depicting thickness of film deposited over particular numbers of ALD cycles for deposition on a tungsten surface and a silicon oxide surface exposed to dimethyldichlorosilane.

FIG. 7 is a graph depicting thickness of film deposited over particular numbers of ALD cycles for deposition on a tungsten surface and a silicon oxide surface exposed to dimethyldichlorosilane and washed with water in accordance with certain disclosed embodiments.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.

Semiconductor manufacturing processes often involve deposition and etching of various materials in a patterning scheme to form specific types of semiconductor devices. Selective deposition of metal oxide films on a dielectric surface in the presence of a metal surface can be achieved, such as by depositing aluminum oxide by atomic layer deposition (ALD) on silicon oxide in the presence of a copper surface. However, the opposite process of selectively depositing a dielectric by ALD on a metal surface in the presence of a silicon oxide surface faces challenges—in particular, the lack of selective inhibitor molecules shifts techniques to other masking techniques rather than using selective deposition techniques. For example, selectively depositing aluminum oxide by ALD on a copper surface in the presence of an exposed silicon oxide surface can be challenging.

Provided herein are methods of selectively depositing material on a metal surface relative to a dielectric surface. Certain disclosed embodiments involve utilizing the reactivity of a metal-oxygen-silicon (M-O—Si) bond versus a silicon-oxygen-silicon (Si—O—Si) bond in water to achieve selective removal of a blocking reagent from a metal surface while blocking reagent remains on a dielectric surface. Certain disclosed embodiments may be particularly suitable for selectively depositing dielectric on metal relative to dielectric surfaces.

For example, disclosed embodiments may involve depositing silicon oxide (e.g., SiO₂), silicon nitride (SiN), carbon-doped silicon nitride, aluminum oxide (Al₂O₃), silicon oxycarbides, silicon carbonitrides, and silicon oxycarbonitrides on metal-containing surfaces such as metal surfaces or metal alloy surfaces. Example metals include tungsten, titanium, aluminum, and copper. A non-limiting example of a silicon oxycarbide is a silicon oxycarbide having the chemical formula SiO_(x)C_(y) where 2x+4y=4 (x and y need not be integers). A non-limiting example of a silicon carbonitride is a silicon carbonitride having the chemical formula SiC_(a)N_(b) where 4a+3b=4 (x and y need not be integers). A non-limiting example of a silicon oxycarbonitride is a silicon oxycarbonitride having the chemical formula SiO_(i)C_(j)N_(k) where 2i+4j+3k=4.

Techniques described herein may involve thermal atomic layer deposition (ALD) and/or plasma-enhanced atomic layer deposition (PEALD). That is, in various embodiments, the reaction between a silicon-containing precursor and an oxidizing agent to form silicon oxide is performed.

ALD is a technique that deposits thin layers of material using sequential self-limiting reactions. Typically, an ALD cycle includes operations to deliver and adsorb at least one reactant to the substrate surface, and then react the adsorbed reactant with one or more reactants to form the partial layer of film. As an example, a silicon oxide deposition cycle may include the following operations: (i) delivery/adsorption of a silicon-containing precursor, (ii) purging of the silicon precursor from the chamber, (iii) delivery of an oxygen-containing reactant or oxygen-containing gas, and (iv) purging of the oxygen-containing reactant from the chamber. In a PEALD process, delivery of the oxygen-containing reactant may be accompanied by generation of a plasma in the oxygen-containing reactant environment.

Unlike a chemical vapor deposition (CVD) technique, ALD processes use surface-mediated deposition reactions to deposit films on a layer-by-layer basis. In one example of an ALD process, a substrate surface that includes a population of surface active sites is exposed to a gas phase distribution of a first precursor, such as a silicon-containing precursor, in a dose provided to a chamber housing a substrate. Molecules of this first precursor are adsorbed onto the substrate surface, including chemisorbed species and/or physisorbed molecules of the first precursor. It should be understood that when the compound is adsorbed onto the substrate surface as described herein, the adsorbed layer may include the compound as well as derivatives of the compound. For example, an adsorbed layer of a silicon-containing precursor may include the silicon-containing precursor as well as derivatives of the silicon-containing precursor. After a first precursor dose, the chamber is then evacuated to remove most or all of first precursor remaining in gas phase so that mostly or only the adsorbed species remain. In some implementations, the chamber may not be fully evacuated. For example, the chamber may be evacuated such that the partial pressure of the first precursor in gas phase is sufficiently low to mitigate a reaction. A second reactant, such as an oxygen-containing reactant, is introduced to the chamber so that some of these molecules react with the first precursor adsorbed on the surface. In some processes, the second reactant reacts immediately with the adsorbed first precursor. The chamber may then be evacuated again to remove unbound second reactant molecules. As described above, in some embodiments the chamber may not be completely evacuated. Additional ALD cycles may be used to build film thickness.

In certain embodiments, an ALD first precursor dose partially saturates the substrate surface. In some embodiments, the dose phase of an ALD cycle concludes before the precursor contacts the substrate to evenly saturate the surface. Typically, the precursor flow is turned off or diverted at this point, and only purge gas flows. By operating in this sub-saturation regime, the ALD process reduces the cycle time and increases throughput. However, because precursor adsorption is not saturation limited, the adsorbed precursor concentration may vary slightly across the substrate surface. Examples of ALD processes operating in the sub-saturation regime are provided in U.S. patent application Ser. No. 14/061,587 (now U.S. Pat. No. 9,355,839), filed Oct. 23, 2013, titled “SUB-SATURATED ATOMIC LAYER DEPOSITION AND CONFORMAL FILM DEPOSITION,” which is incorporated herein by reference in its entirety.

As described, in some implementations, the ALD methods include plasma activation. As described herein, the ALD methods and apparatuses described herein may be conformal film deposition (CFD) methods, which are described generally in U.S. patent application Ser. No. 13/084,399 (now U.S. Pat. No. 8,728,956), filed Apr. 11, 2011, and titled “PLASMA ACTIVATED CONFORMAL FILM DEPOSITION,” and in U.S. patent application Ser. No. 13/084,305, filed Apr. 11, 2011, and titled “SILICON NITRIDE FILMS AND METHODS,” which are herein incorporated by reference in their entireties.

Selective blocking of one surface relative to another can be achieved using a two-step process. The first operation is non-selective adsorption of an inhibitor molecule. The second operation is selective removal of the inhibitor molecule from one surface via a wet etch using pure water or another hydrolyzing agent which hydrolyzes the chemical bond attaching the inhibitor molecule to one surface and not the other. This method may be performed such that one surface is silicon-based and the other is metal-based. The deposition method to be used after net-inhibition may be atomic layer deposition of a metal oxide film.

Selective deposition of metal oxide films on a dielectric surface in the presence of a metal surface may be performed using deposition of ALD alumina on a dielectric such as silicon oxide in the presence of a tungsten or copper or other metal surface. However, inhibitors used in selective deposition to deposit on dielectric may not be selective to the metal surface due to the hydroxyl termination found on typical dielectric surfaces.

Certain disclosed embodiments involve the opposite; selective deposition of ALD alumina on a tungsten or copper or other metal surface in the presence of a dielectric surface.

Some ALD dielectric deposition involves a metal organic precursor (tri-methyl-aluminum or tetrakis (dimethylamido) zirconium for example) and water to deposit a film. An ALD cycle may include an exposure of the metal organic precursor to the surface where native hydroxyls or oxide species react with the precursor to form surface-oxygen-metal bonds displacing one of the metal organic ligands as either an amine (e.g. HN(CH₃)₂) or as a hydrocarbon (e.g. CH₄). A method to block deposition on a surface is to eliminate these reactive hydroxyls/oxides (surface-OH or surface=O) and replace them with hydrocarbon termination (surface —CxHy). Regents such as silicon amides (e.g. Si(CH₃)₃(NMe₂)) readily perform this reaction but are non-selective.

One solution to this problem of non-selectivity is to eliminate the oxides on the metal surface via reduction such as described elsewhere herein. This method involves selective deposition on the dielectric and not on the metal.

To achieve selective deposition on the metal and not on the dielectric, one embodiment involves non-selectively reacting alkylation reagents such as silicon amides to both dielectric and metal surfaces and then selectively removing the reagent to form the metal surface using water. Water readily hydrolyzes the bond between the inhibitor and the metal surface (e.g. M-O—Si(CH₃)₃+H₂O-->M-OH+HO—Si(CH₃)₃) but does not readily cause the same reaction on the dielectric surface.

Selective growth of metal oxide on a metal surface and not on a dielectric surface can be performed by selectively blocking the dielectric surface using certain disclosed embodiments.

FIG. 1 provides a process flow diagram depicting operations in a method performed in accordance with certain disclosed embodiments. Processing temperatures that may be suitable for certain disclosed embodiments depend on the technique used for each operation. Some embodiments for some operations described herein may be performed at temperatures between about 70° C. and about 200° C., or between about 100° C. and about 150° C.

In operation 101, a substrate having an exposed metal surface and an exposed dielectric surface is provided. The substrate may be a silicon wafer, e.g., a 200-mm wafer, a 300-mm wafer, or a 450-mm wafer, including wafers having one or more layers of material, such as dielectric, conducting, or semi-conducting material deposited thereon. Non-limiting examples of under-layers include dielectric layers and conducting layers; materials include but are not limited to silicon oxides, silicon nitrides, silicon carbides, metal oxides, metal nitrides, metal carbides, and metals. The substrate may be patterned in some embodiments. The substrate may not be patterned in some embodiments. In some embodiments, the substrate includes a dielectric material and vias filled with a metal (such as interconnect lines).

In various embodiments, the dielectric material may be a silicon-containing material, such as silicon oxide, silicon nitride, carbon-doped silicon oxide, or combinations thereof. In various embodiments, the dielectric material may be an ultra-low k (ULK) dielectric. In some embodiments, the dielectric material may be a semiconductor material instead of a dielectric material. In various embodiments, the dielectric layer includes hydroxyl-terminated silicon oxide.

In various embodiments, the exposed metal surface includes one or more of the following metals or its alloys: tungsten, aluminum, titanium, titanium aluminum, and combinations thereof.

In some embodiments, the substrate is patterned with vias which are filled with a metal such as copper. In some embodiments, the vias are filled with copper oxides, ruthenium, and/or ruthenium oxides. In some embodiments, the copper is reduced using exposure to a reducing agent such as hydrogen or hydrazine to prepare the service for subsequent operations.

FIG. 2A is a schematic illustration of an example substrate having an exposed silicon oxide surface 201 and an exposed metal surface 203.

Returning to FIG. 1, in operation 103, the substrate is exposed to a blocking reagent that adsorbs, or deposits onto both the metal and dielectric surfaces, regardless of surface chemistry or topography. In some embodiments, a blocking reagent both adsorbs and deposits onto the metal and dielectric surfaces.

FIG. 2B is a schematic illustration of an example substrate having an exposed silicon oxide surface 201 and exposed metal surface 203 where the blocking reagent adsorbs onto both surfaces to form blocked surface 205 having adsorbed blocking reagent 207 having Si—O—Si bonds on the dielectric and adsorbed blocking reagent 209 having M-O—Si bonds on the metal.

It will be understood that although a flat surface is depicted in this figure, certain disclosed embodiments may be applicable to surfaces having topography including features of various sizes and heights. Example features include holes, trenches, vias, and other features. The substrate is exposed to a blocking reagent which reacts with both the exposed metal surface and dielectric material. The blocking reagent may be one or more alkylation reagents such as silicon amides. The blocking reagent is reactive with both dielectric and metal surfaces alike, but are removable from metal surfaces using hydrolysis and not removable from dielectric surfaces using hydrolysis.

The blocking reagent may be any chemical compound capable of forming a hydrolyzable bond with a metal surface and a nonhydrolyzable bond with a dielectric surface. In various embodiments, the blocking reagent forms a hydrolyzable bond with metal. In various embodiments, the blocking reagent is capable of forming a metal-oxygen-silicon bond with the metal, and is capable of forming a silicon-oxygen-silicon bond with a silicon-containing dielectric material.

Example blocking reagents include alkylaminosilanes, and alkylchlorosilanes. Alkylaminosilanes may be used in some embodiments because resulting byproducts from later hydrolysis and selective deposition on metal yields byproducts that may be less damaging to surfaces of the semiconductor substrate as compared to byproducts of hydrolysis involving alkylchlorosilanes, which may form hydrogen chloride (HCl) which is potentially damaging to surfaces of the substrate.

A suitable alkylaminosilane can have the general chemical formula of [(CH₃)₂N]_(x)Si([CH₃(CH₂)_(y)])_((4-x)), where x is an integer between and including 1 and 3, and y is any integer greater than or equal to 1.

A suitable alkylchlorosilane can have the general chemical formula of Cl_(x)Si([CH₃(CH₂)_(y)])_((4-x)), where x is an integer between and including 1 and 3, and y is any integer greater than or equal to 1.

One example alkylchlorosilane that may be used is dimethyldichlorosilane.

Exposure to the blocking reagent may be performed using one of the following techniques: a wet technique and a dry technique. A wet technique may involve dipping the substrate in a solution having the blocking reagent therein to expose the surfaces of the substrate to the blocking reagent or using a spin coater to deliver the solution having the blocking reagent to the surface of the substrate.

Where an alkylaminosilane or alkylchlorosilane is used as the blocking reagent, the solution having the blocking reagent is a nonaqueous polar solvent. The solvent may be an aprotic polar solvent in various embodiments. Examples of solvents for an alkylaminosilane that may be suitable include dimethylformamide (DMF), diethylether, and acetylnitrile:

An example of a solvent for an alkylchlorosilane includes propylene glycol methyl ether (PGME):

Other potential solvents include alcohols.

A dry technique may involve preparing the blocking reagent in a vapor or gas phase and delivering the vapor phase or gas phase blocking reagent to a chamber housing the substrate to expose the substrate surface to the blocking reagent.

Suitable temperatures that may be used for this operation depend on the technique selected and is limited by thermal decomposition of the blocking reagent. For the wet technique, the solution may be heated or cooled to a temperature of about room temperature, or about 25° C., or at least about room temperature, or at least about 60° C., or between about 25° C. and about 100° C., or between about 60° C. and about 100° C. For the dry technique, the substrate may be held on a pedestal set to a temperature of a temperature greater than that for which thermal decomposition of the blocking reagent occurs. In various embodiments, the temperature may be between about 100° C. and about 300° C., or between about 200° C. and about 250° C.

Operation 103 may be performed for a duration between about 10 seconds and about 60 seconds.

Returning to FIG. 1, in operation 105, a chamber housing the substrate may be optionally purged to remove excess blocking reagent. Purging the chamber may involve flowing a purge gas or a sweep gas, which may be a carrier gas used in other operations or may be a different gas. In some embodiments, purging may involve evacuating the chamber. However, in some embodiments, the chamber is not evacuated. Example purge gases include, but are not limited to, argon, nitrogen, hydrogen, and helium. In some embodiments, operation 105 may include one or more evacuation subphases for evacuating the process chamber. Alternatively, it will be appreciated that operation 105 may be omitted in some embodiments. Operation 105 may have any suitable duration, such as between about 0 seconds and about 60 seconds, for example about 0.01 seconds. In some embodiments, increasing a flow rate of one or more purge gases may decrease the duration of operation 105. For example, a purge gas flow rate may be adjusted according to various reactant thermodynamic characteristics and/or geometric characteristics of the process chamber and/or process chamber plumbing for modifying the duration of operation 105. In one non-limiting example, the duration of a purge phase may be adjusted by modulating purge gas flow rate. This may reduce deposition cycle time, which may improve substrate throughput. After a purge, the blocking reagent remains adsorbed onto both the metal and dielectric surfaces.

In operation 107, the blocking reagent is selectively removed from the metal surface. In some embodiments, this operation involves contacting the substrate with water. In various embodiments, contacting the substrate with water may be performed by dipping the substrate in water, or delivering water to the surface of the substrate. In various embodiments, the substrate surface is hydrolyzed to selectively remove the blocking reagent from the metal surface relative to the dielectric material such that the blocking reagent remains on the dielectric material and the metal surface is exposed. Hydrolyzing can be performed by dipping the substrate in a container of water. Operation 107 may be performed at room temperature. Hydrolyzing is not performed using water vapor or gas phase techniques. In some embodiments, an aqueous hydrolysis technique is used.

Hydrolyzing may be performed at room temperature or any temperature greater than room temperature. Dipping the substrate at room temperature hydrolyzes the blocking reagent, thereby cleaving the metal-oxygen-silicon bond on metal surfaces in a matter of seconds. Since the silicon-oxygen-silicon bonds are not hydrolyzable and not reactive with water, the blocking reagent remains on dielectric surfaces, thereby resulting in a substrate having blocking reagent selectively on dielectric material relative to exposed metal surfaces.

Without being bound by a particular theory, it is believed that dipping in water results in a hydrogen-terminated or hydroxyl-terminated metal surface, which is susceptible to subsequent deposition while the blocking reagent that remains on the dielectric surface is not susceptible to subsequent deposition.

In operation 807-818, metal oxide (such as alumina) may be selectively deposited onto the exposed metal surface relative to the dielectric surface. For example, ALD may be performed whereby the deposition precursor selectively adsorbs onto the exposed metal surface and an oxidant is used to selectively form metal oxide on the exposed metal surface. For example, alumina deposited by ALD may involve using a deposition precursor such as trimethylaluminum.

FIG. 2C is a schematic illustration of an example substrate whereby water is introduced to the substrate having adsorbed blocked surface 205 having adsorbed blocking reagent 207 having Si—O—Si bonds on the dielectric and adsorbed blocking reagent 209 having M-O—Si bonds on the metal.

FIG. 2D is a schematic illustration of an example substrate whereby hydrogen cleaves the hydrolyzable bonds between the blocking reagent 209 on the metal and the metal surface, resulting in a hydroxyl-terminated metal surface 211.

FIG. 2E is a schematic illustration of an example substrate whereby adsorbed blocking reagent is removed from the metal surface by hydrolysis while the adsorbed blocking reagent 207 remains on the dielectric surface, resulting in hydroxyl-terminated metal surface 213, which is ready for deposition of, for example, a metal oxide material.

FIG. 3 provides a timing schematic diagram of various operations performed in accordance with certain disclosed embodiments. Although process 300 depicted in FIG. 3 includes only two deposition cycles 399A and 399B, it will be understood that more than two deposition cycles (and in some cases, only one deposition cycle) may be performed in certain disclosed embodiments.

FIG. 3 shows phases in an example deposition process 300, for various process parameters, such as flow of argon as a carrier gas and/or purge gas, blocking reagent gas flow, water flow (used herein as a dip process, not a gaseous process), metal precursor gas flow, oxygen-containing reactant exposure, and reducing agent gas flow. Although the example depicts ALD using an oxygen-containing reactant as the deposition technique and plasma is not depicted in FIG. 3, in some embodiments an oxygen-containing plasma may be used to deposit metal oxide such that plasma is generated when oxygen-containing reactant is flowed. The lines in FIG. 3 indicate when the flow is turned on and off and when the water dip is performed. Various disclosed embodiments depend on process parameters that include, but are not limited to, flow rates for inert, blocking reagent, and reactant species, flow rates for argon as a carrier gas, metal precursor, and oxygen-containing gases, substrate temperature, and process chamber pressure.

As depicted in FIG. 3, prior to selective deposition, a blocking reagent exposure phase 303 is performed whereby blocking reagent is delivered, while metal precursor and oxygen-containing reactant flows are off. The blocking reagent can be delivered using argon gas in this example. Water is not used; it will be understood that water as depicted in FIG. 3 refers to dipping the substrate in water, not introducing water in gas or vapor phase. This may correspond to operation 103 of FIG. 1.

Water dip 307 is performed whereby the substrate is dipped in an aqueous bath of water. It will be understood that this may be performed in a matter of seconds and may be performed at room temperature. In some cases, this may be performed at a higher temperature, but dipping the wafer at room temperature can achieve a quick hydrolysis reaction in a few seconds without substantially prolonging the overall process time. Although argon is depicted as being in an “on” phase, the substrate may be taken out of a chamber to be dipped and then subsequently placed back into a chamber. This may correspond to operation 107 of FIG. 1.

Deposition cycle 339A may correspond to operation 111 of FIG. 1. In some embodiments, deposition cycle 339 includes a cyclic deposition process as depicted in FIG. 3. Deposition cycle 399A includes metal precursor exposure phase 311-1A, purge phase 311-2A, oxygen-containing reactant exposure phase 311-3A, and purge phase 311-4A. During silicon-containing precursor exposure phase 311-1A, argon flow may be on to assist delivery of the metal precursor, while blocking reagent flow is off, metal precursor flow is on, and oxygen-containing reactant flow is off. In purge phase 311-2A, all gas flows and plasmas are off except argon gas flow, which acts as a purge gas. In oxygen-containing reactant exposure phase 311-3A, argon flow may continue to be on, blocking reagent flow is off, metal precursor gas flow is off, and oxygen-containing reactant flow is on. In purge phase 311-4A, argon flow is on to act as a purge gas, while blocking reagent flow is off, metal precursor gas flow is off, and oxygen-containing reactant flow is off. In this example, it is determined that metal oxide is not deposited to the desired thickness, so the operations are repeated in deposition cycle 399B. Deposition cycle 399B metal precursor exposure phase 311-1B, where only argon and metal precursor gas flows are on while blocking reagent gas flow, and oxygen-containing reactant gas flow are off; purge phase 311-2B whereby only argon is flowed as a purge gas; oxygen-containing reactant exposure phase 311-3B whereby only argon and oxygen-containing reactant are on while blocking reagent, and metal precursor gas flows are off; and purge phase 311-4B whereby argon is flowed as a purge gas.

Apparatus

FIG. 4 depicts a schematic illustration of an embodiment of an atomic layer deposition (ALD) process station 400 having a process chamber body 402 for maintaining a low-pressure environment. Such tool may be used to deliver a blocking reagent as well as to deposit a metal oxide film after dipping the substrate having the blocking reagent in water.

A plurality of ALD process stations 400 may be included in a common low pressure process tool environment. For example, FIG. 5 depicts an embodiment of a multi-station processing tool 500. In some embodiments, one or more hardware parameters of ALD process station 400 including those discussed in detail below may be adjusted programmatically by one or more computer controllers 450.

ALD process station 400 fluidly communicates with reactant delivery system 401 a for delivering process gases to a distribution showerhead 406. Reactant delivery system 401 a includes a mixing vessel 404 for blending and/or conditioning process gases, such as a blocking reagent gas, metal precursor gas, or oxygen-containing gas for delivery to showerhead 406. One or more mixing vessel inlet valves 420 may control introduction of process gases to mixing vessel 404.

As an example, the embodiment of FIG. 4 includes a vaporization point 403 for vaporizing liquid reactant to be supplied to the mixing vessel 404. In some embodiments, vaporization point 403 may be a heated vaporizer. The saturated reactant vapor produced from such vaporizers may condense in downstream delivery piping. Exposure of incompatible gases to the condensed reactant may create small particles. These small particles may clog piping, impede valve operation, contaminate substrates, etc. Some approaches to addressing these issues involve purging and/or evacuating the delivery piping to remove residual reactant. However, purging the delivery piping may increase process station cycle time, degrading process station throughput. Thus, in some embodiments, delivery piping downstream of vaporization point 403 may be heat traced. In some examples, mixing vessel 404 may also be heat traced. In one non-limiting example, piping downstream of vaporization point 403 has an increasing temperature profile extending from approximately 100° C. to approximately 150° C. at mixing vessel 404.

In some embodiments, liquid precursor or liquid reactant may be vaporized at a liquid injector. For example, a liquid injector may inject pulses of a liquid reactant into a carrier gas stream upstream of the mixing vessel. In one embodiment, a liquid injector may vaporize the reactant by flashing the liquid from a higher pressure to a lower pressure. In another example, a liquid injector may atomize the liquid into dispersed microdroplets that are subsequently vaporized in a heated delivery pipe. Smaller droplets may vaporize faster than larger droplets, reducing a delay between liquid injection and complete vaporization. Faster vaporization may reduce a length of piping downstream from vaporization point 403. In one scenario, a liquid injector may be mounted directly to mixing vessel 404. In another scenario, a liquid injector may be mounted directly to showerhead 406.

In some embodiments, a liquid flow controller (LFC) upstream of vaporization point 403 may be provided for controlling a mass flow of liquid for vaporization and delivery to process station 400. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. A plunger valve of the LFC may then be adjusted responsive to feedback control signals provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM. However, it may take one second or more to stabilize liquid flow using feedback control. This may extend a time for dosing a liquid reactant. Thus, in some embodiments, the LFC may be dynamically switched between a feedback control mode and a direct control mode. In some embodiments, this may be performed by disabling a sense tube of the LFC and the PID controller.

Showerhead 406 distributes process gases toward substrate 412. In the embodiment shown in FIG. 4, the substrate 412 is located beneath showerhead 406 and is shown resting on a pedestal 408. Showerhead 406 may have any suitable shape, and may have any suitable number and arrangement of ports for distributing process gases to substrate 412.

In some embodiments, pedestal 408 may be raised or lowered to expose substrate 412 to a volume between the substrate 412 and the showerhead 406. It will be appreciated that, in some embodiments, pedestal height may be adjusted programmatically by a suitable computer controller 450.

In another scenario, adjusting a height of pedestal 408 may allow a plasma density to be varied during plasma activation cycles in the process in embodiments where a plasma is ignited. At the conclusion of the process phase, pedestal 408 may be lowered during another substrate transfer phase to allow removal of substrate 412 from pedestal 408.

In some embodiments, pedestal 408 may be temperature controlled via heater 410. In some embodiments, the pedestal 408 may be heated to a temperature of between about 70° C. and about 200° C., or between about 100° C. and about 120° C.

Further, in some embodiments, pressure control for process station 400 may be provided by butterfly valve 418. As shown in the embodiment of FIG. 4, butterfly valve 418 throttles a vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of process station 400 may also be adjusted by varying a flow rate of one or more gases introduced to the process station 400.

In some embodiments, a position of showerhead 406 may be adjusted relative to pedestal 408 to vary a volume between the substrate 412 and the showerhead 406. Further, it will be appreciated that a vertical position of pedestal 408 and/or showerhead 406 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, pedestal 408 may include a rotational axis for rotating an orientation of substrate 412. It will be appreciated that, in some embodiments, one or more of these example adjustments may be performed programmatically by one or more suitable computer controllers 450.

In some embodiments where plasma may be used as discussed above, showerhead 406 and pedestal 408 electrically communicate with a radio frequency (RF) power supply 414 and matching network 416 for powering a plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of a process station pressure, a gas concentration, an RF source power, an RF source frequency, and a plasma power pulse timing. For example, RF power supply 414 and matching network 416 may be operated at any suitable power to form a plasma having a desired composition of radical species. Examples of suitable powers are about 150 W to about 6000 W. Plasma may be used during treatment of a silicon nitride surface prior to selective deposition of silicon oxide on silicon oxide relative to silicon nitride. RF power supply 414 may provide RF power of any suitable frequency. In some embodiments, RF power supply 414 may be configured to control high- and low-frequency RF power sources independently of one another. Example low-frequency RF frequencies may include, but are not limited to, frequencies between 0 kHz and 500 kHz. Example high-frequency RF frequencies may include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz, or greater than about 13.56 MHz, or greater than 27 MHz, or greater than 40 MHz, or greater than 60 MHz. It will be appreciated that any suitable parameters may be modulated discretely or continuously to provide plasma energy for the surface reactions.

In some embodiments, the plasma may be monitored in-situ by one or more plasma monitors. In one scenario, plasma power may be monitored by one or more voltage, current sensors (e.g., VI probes). In another scenario, plasma density and/or process gas concentration may be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters may be programmatically adjusted based on measurements from such in-situ plasma monitors. For example, an OES sensor may be used in a feedback loop for providing programmatic control of plasma power. It will be appreciated that, in some embodiments, other monitors may be used to monitor the plasma and other process characteristics. Such monitors may include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure transducers.

In some embodiments, instructions for a controller 450 may be provided via input/output control (IOC) sequencing instructions. In one example, the instructions for setting conditions for a process phase may be included in a corresponding recipe phase of a process recipe. In some cases, process recipe phases may be sequentially arranged, so that all instructions for a process phase are executed concurrently with that process phase. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe phase. For example, a first recipe phase may include instructions for setting a flow rate of an blocking reagent gas such as an alkylaminosilane or an alkylchlorosilane, instructions for setting a flow rate of a carrier gas (such as argon), and time delay instructions for the first recipe phase. In some embodiments, the substrate is removed from the chamber after the first recipe phase to dip it in a water bath and selectively remove blocking reagent from the metal surface before replacing the substrate in the chamber for a second recipe phase. A second recipe phase may include instructions for setting a flow rate of an inert and/or metal precursor gas, instructions for setting a flow rate of a carrier gas (such as argon), and time delay instructions for a second recipe phase. A third, subsequent recipe phase may include instructions for modulating or stopping a flow rate of an inert and/or a reactant gas, and instructions for modulating a flow rate of a carrier or purge gas and time delay instructions for the third recipe phase. A fourth recipe phase may include instructions for modulating a flow rate of an oxygen-containing gas, instructions for modulating the flow rate of a carrier or purge gas, and time delay instructions for the fourth recipe phase. A fifth, subsequent recipe phase may include instructions for modulating or stopping a flow rate of an inert and/or a reactant gas, and instructions for modulating a flow rate of a carrier or purge gas and time delay instructions for the fifth recipe phase. It will be appreciated that these recipe phases may be further subdivided and/or iterated in any suitable way within the scope of the disclosed embodiments. In some embodiments, the controller 450 may include any of the features described below with respect to system controller 550 of FIG. 5.

As described above, one or more process stations may be included in a multi-station processing tool. FIG. 5 shows a schematic view of an embodiment of a multi-station processing tool 500 with an inbound load lock 502 and an outbound load lock 504, either or both of which may include a remote plasma source. A robot 506 at atmospheric pressure is configured to move wafers from a cassette loaded through a pod 508 into inbound load lock 502 via an atmospheric port 510. A wafer is placed by the robot 506 on a pedestal 512 in the inbound load lock 502, the atmospheric port 510 is closed, and the load lock is pumped down. Further, the wafer also may be heated in the inbound load lock 502 as well, for example, to remove moisture and adsorbed gases. Next, a chamber transport port 516 to processing chamber 514 is opened, and another robot (not shown) places the wafer into the reactor on a pedestal of a first station shown in the reactor for processing. While the embodiment depicted in FIG. 5 includes load locks, it will be appreciated that, in some embodiments, direct entry of a wafer into a process station may be provided.

The depicted processing chamber 514 includes four process stations, numbered from 1 to 4 in the embodiment shown in FIG. 5. Each station has a heated pedestal (shown at 518 for station 1), and gas line inlets. It will be appreciated that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, a process station may be switchable between an ALD and plasma-enhanced ALD process mode. Additionally or alternatively, in some embodiments, processing chamber 514 may include one or more matched pairs of ALD and plasma-enhanced ALD process stations. While the depicted processing chamber 514 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments a processing chamber may have three or fewer stations.

FIG. 5 depicts an embodiment of a wafer handling system 590 for transferring wafers within processing chamber 514. In some embodiments, wafer handling system 590 may transfer wafers between various process stations and/or between a process station and a load lock. It will be appreciated that any suitable wafer handling system may be employed. Non-limiting examples include wafer carousels and wafer handling robots. FIG. 5 also depicts an embodiment of a system controller 550 employed to control process conditions and hardware states of process tool 500. System controller 550 may include one or more memory devices 556, one or more mass storage devices 554, and one or more processors 552. Processor 552 may include a CPU or computer, analog, and/or digital input/output connections, stepper motor controller boards, etc.

In some embodiments, system controller 550 controls all of the activities of process tool 500. System controller 550 executes system control software 558 stored in mass storage device 554, loaded into memory device 556, and executed on processor 552. Alternatively, the control logic may be hard coded in the controller 550. Applications Specific Integrated Circuits, Programmable Logic Devices (e.g., field-programmable gate arrays, or FPGAs) and the like may be used for these purposes. In the following discussion, wherever “software” or “code” is used, functionally comparable hard coded logic may be used in its place. System control software 558 may include instructions for controlling the timing, mixture of gases, gas flow rates, chamber and/or station pressure, chamber and/or station temperature, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and/or susceptor position, and other parameters of a particular process performed by process tool 500. System control software 558 may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control operation of the process tool components used to carry out various process tool processes. System control software 558 may be coded in any suitable computer readable programming language.

In some embodiments, system control software 558 may include input/output control (IOC) sequencing instructions for controlling the various parameters described above. Other computer software and/or programs stored on mass storage device 554 and/or memory device 556 associated with system controller 550 may be employed in some embodiments. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

A substrate positioning program may include program code for process tool components that are used to load the substrate onto pedestal 518 and to control the spacing between the substrate and other parts of process tool 500.

A process gas control program may include code for controlling gas composition (e.g., blocking reagent gases such as alkylaminosilanes or alkylchlorosilanes, metal precursor gases, and oxygen-containing gases, carrier gases and/or purge gases as described herein) and flow rates and optionally for flowing gas into one or more process stations prior to deposition in order to stabilize the pressure in the process station. A pressure control program may include code for controlling the pressure in the process station by regulating, for example, a throttle valve in the exhaust system of the process station, a gas flow into the process station, etc.

A heater control program may include code for controlling the current to a heating unit that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas (such as helium) to the substrate.

A plasma control program may include code for setting RF power levels applied to the process electrodes in one or more process stations in accordance with the embodiments herein.

A pressure control program may include code for maintaining the pressure in the reaction chamber in accordance with the embodiments herein.

In some embodiments, there may be a user interface associated with system controller 550. The user interface may include a display screen, graphical software displays of the apparatus and/or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.

In some embodiments, parameters adjusted by system controller 550 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels), etc. These parameters may be provided to the user in the form of a recipe, which may be entered utilizing the user interface.

Signals for monitoring the process may be provided by analog and/or digital input connections of system controller 550 from various process tool sensors. The signals for controlling the process may be output on the analog and digital output connections of process tool 500. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

System controller 550 may provide program instructions for implementing the above-described deposition processes. The program instructions may control a variety of process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control the parameters to operate in-situ deposition of film stacks according to various embodiments described herein.

The system controller 550 will typically include one or more memory devices and one or more processors configured to execute the instructions so that the apparatus will perform a method in accordance with disclosed embodiments. Machine-readable media containing instructions for controlling process operations in accordance with disclosed embodiments may be coupled to the system controller 550.

In some implementations, the system controller 550 is part of a system, which may be part of the above-described examples. Such systems can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The system controller 550, depending on the processing conditions and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system.

Broadly speaking, the system controller 550 may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the system controller 550 in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.

The system controller 550, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the system controller 550 may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the system controller 550 receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the system controller 550 is configured to interface with or control. Thus as described above, the system controller 550 may be distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.

As noted above, depending on the process step or steps to be performed by the tool, the system controller 550 might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.

An appropriate apparatus for performing the methods disclosed herein is further discussed and described in U.S. patent application Ser. No. 13/084,399 (now U.S. Pat. No. 8,728,956), filed Apr. 11, 2011, and titled “PLASMA ACTIVATED CONFORMAL FILM DEPOSITION”; and Ser. No. 13/084,305, filed Apr. 11, 2011, and titled “SILICON NITRIDE FILMS AND METHODS,” each of which is incorporated herein in its entireties.

The apparatus/process described herein may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels and the like. Typically, though not necessarily, such tools/processes will be used or conducted together in a common fabrication facility. Lithographic patterning of a film typically includes some or all of the following operations, each operation enabled with a number of possible tools: (1) application of photoresist on a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

EXPERIMENTAL Experiment 1

An experiment was conducted to compare deposition growth on blocked versus unblocked tungsten and silicon oxide surfaces of a substrate. Zirconium oxide was deposited using ALD on a tungsten surface that was not exposed to dimethyldichlorosilane and the number of cycles and thickness deposited are graphed in FIG. 6A as solid plots and a solid line. Zirconium oxide was deposited on a tetraethyl orthosilicate-based silicon oxide surface that was not exposed to dimethyldichlorosilane by ALD and the number of cycles and thickness deposited are graphed in FIG. 6A as the open plots and a dotted line. As shown, growth trends of both films are similar and growth increases at approximately the same rate for both.

Subsequently, a tungsten substrate was first exposed to dimethyldichlorosilane and subsequently, zirconium oxide was deposited on the dimethyldichlorosilane-exposed tungsten substrate using the same ALD cycles as in FIG. 6A. The number of cycles and thickness deposited are graphed in FIG. 6B as solid plots and a solid line. Likewise, a silicon oxide substrate was first exposed to dimethyldichlorosilane and subsequently, zirconium oxide was deposited on the dimethyldichlorosilane-exposed silicon oxide substrate using the same ALD cycles as in FIG. 6A. The number of cycles and thickness deposited are graphed in FIG. 6B as the open plots and a dotted line. As shown, growth of both films is similar to each other, and growth increases at approximately the same rate for both surfaces, but overall deposition thickness for both surfaces compared to FIG. 6A is substantially less—in fact, in the first 10 cycles of ALD, there appears to be little, if any deposition on either of the dimethyldichlorosilane-exposed substrates. The zirconium oxide thickness remains less than 10 even at 30 cycles of ALD. These results suggest dimethyldichlorosilane inhibits deposition on both tungsten and silicon oxide surfaces alike.

A substrate having an exposed tungsten surface was exposed to dimethyldichlorosilane and then dipped in water before zirconium oxide was deposited using ALD cycles as in FIG. 6A. The number of cycles and thickness deposited are graphed in FIG. 7 as solid plots and a solid line. Additionally, a substrate having an exposed silicon oxide surface was exposed to dimethyldichlorosilane and then dipped in water before zirconium oxide was deposited using ALD cycles as in FIG. 6A. The number of cycles and thickness deposited are graphed in FIG. 7 as the open plots and a dotted line. As shown in FIG. 7, the initiation of zirconium oxide deposition occurs much sooner on the tungsten surface than on the silicon oxide surface. Further, the zirconium oxide deposition growth is similar to that of FIG. 6A, which suggests that dipping in a water bath removed the inhibitor from the tungsten surface such that zirconium oxide could be deposited. Meanwhile, silicon oxide growth is similar to silicon oxide growth in FIG. 6B, which suggests that dipping in the water bath did not remove the inhibitor from the silicon oxide surface, and thus the silicon oxide surface remains blocked and less zirconium oxide was deposited on that surface. These results indicate viability of using dimethyldichlorosilane as a blocking reagent to allow selective deposition on a tungsten surface relative to a silicon oxide surface.

CONCLUSION

Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein. 

What is claimed is:
 1. A method of selectively depositing metal oxide on an exposed metal surface relative to a dielectric material on a substrate, the method comprising: (a) providing the substrate comprising the dielectric material and the exposed metal surface; (b) prior to depositing the metal oxide, exposing the substrate to a blocking reagent to non-selectively adsorb the blocking reagent onto both the dielectric material and the exposed metal surface; (c) after exposing the substrate to the blocking reagent and prior to depositing the metal oxide, selectively removing the blocking reagent from the exposed metal surface; and (d) selectively depositing the metal oxide on the exposed metal surface relative to the dielectric material on the substrate; wherein the exposed metal surface comprises a metal selected from the group consisting of tungsten, titanium, and aluminum.
 2. The method of claim 1, wherein selectively removing the blocking reagent is performed by contacting the substrate with water.
 3. The method of claim 1, wherein selectively removing the blocking reagent is performed by dipping the substrate in water.
 4. The method of claim 1, wherein the blocking reagent is a silicon amide, alkylchlorosilane or alkylaminosilane.
 5. The method of claim 4, wherein the alkylchlorosilane has a chemical structure of Cl_(x)Si([CH₃(CH₂)_(y)])_((4-x)), where x is an integer between and including 1 and 3, and y is an integer greater than or equal to
 1. 6. The method of claim 4, wherein the alkylaminosilane has a chemical structure of [(CH₃)₂N]_(x)Si([CH₃(CH₂)_(y)])_((4-x)), where x is an integer between and including 1 and 3, and y is an integer greater than or equal to
 1. 7. The method of claim 1, wherein the blocking reagent forms a hydrolyzable bond with the exposed metal surface but does not form a hydrolyzable bond with the dielectric material.
 8. The method of claim 1, wherein the substrate is exposed to the blocking reagent by dipping the substrate in a wet solution of the blocking reagent.
 9. The method of claim 8, wherein the substrate is exposed to the blocking reagent at a temperature between about 25° C. and about 100° C. or between about 60° C. and about 100° C.
 10. The method of claim 1, wherein the substrate is exposed to the blocking reagent by introducing the blocking reagent in vapor phase.
 11. The method of claim 10, wherein the substrate is exposed to the blocking reagent at a temperature between about 100° C. and about 300° C. or between about 200° C. and about 250° C.
 12. The method of claim 1, wherein the substrate is exposed to the blocking reagent for a duration between about 10 seconds and about 60 seconds.
 13. The method of claim 1, wherein selectively removing the blocking reagent is performed at room temperature.
 14. The method of claim 1, wherein selectively removing the blocking reagent selectively hydrolyzes bonds between the blocking reagent and the exposed metal surface.
 15. The method of claim 1, wherein the metal oxide is alumina.
 16. The method of claim 1, wherein the metal oxide is selectively deposited on the exposed metal surface relative to the dielectric material using atomic layer deposition.
 17. The method of claim 1, wherein the dielectric material comprises silicon.
 18. The method of claim 17, wherein the dielectric material is selected from the group consisting of silicon oxide, silicon nitride, carbon-doped silicon oxide.
 19. The method of claim 1, wherein the substrate is patterned.
 20. The method of claim 1, wherein the hydrolyzing results in the exposed metal surface having a hydrogen-terminated and/or hydroxyl-terminated surface. 